Qsys System Design Tutorial2015.05.04TU-01006SubscribeSend FeedbackThis tutorial introduces you to the Qsys system integration tool available with the

Add the PRBS Pattern CheckerThe PRBS pattern checker performs the opposite operation of the PRBS pattern generator. The processoruses the memory-mappe

Connect the Reset SignalsYou must connect all the reset signals, which eliminates the error messages in the Messages tab. Qsysallows multiple reset do

Figure 2: Top-Level Memory Tester Design with a Processor and SDRAM ControllerNote: The hierarchical system you create is based on the lower-level pat

• Create a Data Pattern Generator Qsys System on page 4• Create a Data Pattern Checker Qsys System on page 8• Qsys Tutorial Design ExampleCreate the H

1. In Qsys, create a new system called, memory_tester_system.2. For the clk instance, turn off Clock frequency is known to indicate that the higher-le

1. In the IP Catalog, double-click pattern_checker_system from the System group.2. In the parameter editor, click Finish to accept the default setting

1. In the IP Catalog, double-click Pattern Reader from the Memory Test Microcores group.2. n the parameter editor, turn on Burst Enable.3. Ensure the

Verify the Memory Address MapTo ensure that the memory map of the system you create matches the memory map of other components,you must verify the bas

by the Nios II processor code or JTAG interface, and also to the Nios II processor's reset inputinterface. The cpu_subsystem cpu_reset interface

5. In the Quartus II software, on the Project menu, click Add/Remove Files in Project and verify that thenewly-generated .qip file, top_system.qip, an

In this tutorial, you instantiate the complete memory tester system in the top-level system along with theprocessor IP Cores, which are grouped as the

Related InformationDownload and Install the Tutorial Design Files on page 3Debugging Your DesignIf the memory test starts but does not complete succes

1. Open the Quartus II project in the project directory for your development board type.2. In Qsys, open top_system.qsys in the project directory for

11.In Qsys, click Tools > System Console.12.Before you execute scripts in System Console, navigate to the directory for the Tcl scripts, and then i

If you do not want to use the Qsys-generated testbench system, you can create your own Qsys testbenchsystem by adding the Avalon Verification Suite Bu

1. In Qsys, open the testbench system, pattern_generator_tb.qsys, from the simulation_tutorial\pattern_generator\testbench directory.2. On the System

This test program performs the following actions:• Reads a pattern file.• Writes the pattern to the design under test via the pattern master BFM.• Set

9. To run the low frequency test, modify \simulation_tutorial\test_include.svh according to Table 4.Table 4: Values for Low Frequency Pattern TestMacr

Related Information• Qsys Tutorial Design Example• Detailed Diagram of the Memory Tester SystemTU-010062015.05.04View a Diagram of the Completed Syste

Software and Hardware RequirementsThe Qsys System Design tutorial requires the following software and hardware requirements:• Altera Quartus II softwa

• Detailed Diagram of the Memory Tester SystemOpen the Tutorial ProjectThe design files for the Qsys tutorial provide the custom IP design blocks that

You must use the exact system names described in this tutorial in order for the provided scripts tofunction correctly.Create a New Qsys System and Set

Add a Custom Pattern GeneratorThe pattern generator generates multiple test patterns to test the off-chip SDRAM device. The custompattern generator sy

You can see the default address range of the pattern_access interface in the Base and End columns on theSystem Contents tab.You assign a base address

7. Connect the two_to_one_st_mux csr interface to the mm_bridge m0 interface.8. Export the two_to_one_st_mux st_output interface with the name st_data

streaming demultiplexer is soft programmable so that the processor can select which pattern checker IPcore should verify the data that the pattern rea