QSC Q-SYS PS-1650G Manual do Utilizador descarregar pdf (Página 5)

You must use the exact system names described in this tutorial in order for the provided scripts to

function correctly.

Create a New Qsys System and Set up the Clock Source

1. In the Quartus II software, click Tools > Qsys to create a new Qsys design.

2. In the System Contents tab, Qsys shows a clock source instance, clk_0. To open the clock source

settings, right-click clk_0, and then click Edit.

3. Turn off Clock frequency is known to indicate that, when created, the higher-level hierarchical system

that instantiates this subsystem provides the clock frequency.

4. Click Finish.

5. Click File > Save As to save the Qsys system.

6. In the Save As dialog box, type pattern_generator_system, and then click Save.

If Qsys prompts you to open the top_system.qsys file, click Cancel in the Open dialog box

Add a Pipeline Bridge

The components that make up the data pattern generator include several Avalon-MM slave interfaces. To

allow a higher-level system to access the Avalon-MM slave interfaces by reading and writing to a single

slave interface, you can consolidate the slave interfaces behind an Avalon-MM pipeline bridge, and export

a single Avalon-MM slave interface out of the system.

To determine the required address width for a bridge, you must know the required addresses span of the

other components in the system. Memory-mapped component interfaces outside the system address each

interface in the system by specifying a memory offset value relative to the base address of the bridge.

A pipeline bridge can also improve system timing performance by optionally adding pipeline registers to

the design.

1. In the Library search box, type bridge to filter the component list and show only bridge components.

2. Select Avalon-MM Pipeline Bridge, and then click Add.

3. In the parameter editor, under Parameters, type 11 for the Address width.

This width accommodates the memory span of all memory-mapped components behind the bridge in

this system. As you add the other components in the system, you specify their base addresses within

the span of the address space.

4. Accept all other default settings, and then click Finish.

The pipeline bridge is added to your system with the instance name mm_bridge_0.

5. On the System Contents tab, right-click mm_bridge_0, click Rename, and then type mm_bridge.

6. In the Clock column for the mm_bridge clk interface, select clk_0 from the list.

7. To export the mm_bridge s0 interface, double-click the Export column, and then type slave.

TU-01006

2015.05.04

Create a New Qsys System and Set up the Clock Source

Qsys System Design Tutorial

Altera Corporation

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QSC Q-SYS PS-1650G Manual do Utilizador Página 5