QSC Q-SYS PS-1650G Manual do Utilizador descarregar pdf (Página 23)

If you do not want to use the Qsys-generated testbench system, you can create your own Qsys testbench

system by adding the Avalon Verification Suite Bus Functional Models (BFMs) or your own models for

simulation. You can also generate a Qsys simulation model for the design or Qsys system under test, and

use your own custom HDL testbench to provide the simulation stimulus.

Related Information

Download and Install the Tutorial Design Files on page 3

Create a New Qsys System for the Design Under Test

1. In the Quartus II software, open the Quartus II Project File, qsys_sim_tutorial.qpf, from the

\simulation_tutorial directory.

2. In Qsys, click File > New System to create a new Qsys design.

3. To remove the clock source, which is not needed for this design, right-click clk_0, and then click

Remove.

4. In the IP Catalog, select Custom Pattern Generator from the Memory Test Microcores group, and

then click Add.

5. In the parameter editor, click Finish to accept the default parameters.

6. Rename the instance to pg to provide a short instance name for the pattern generator.

Export Design Under Test

1. In Qsys, on the System Contents tab, in the Export column, for each interface click Double-click to

export, and maintain the default export names.

2. Save the system as pattern_generator.

Generate a Testbench System

1. In Qsys click Generate > Generate Testbench System.

2. Under Testbench System, for Create testbench Qsys system, select Standard, BFMs for standard

Qsys interfaces.

3. Under Synthesis, select None for Create HDL design files for synthesis, and turn off Create block

symbol file (.bsf).

4. Click Generate.

5. After Qsys generates the testbench, click Close.

Qsys generates this testbench system in the \simulation_tutorial\pattern_generator\testbench directory.

You can generate the simulation model for the Qsys testbench system at the same time by turning on

Create testbench simulation model. However, the Qsys-generated testbench system's components names

are assigned automatically and you may want to control the instance names to make it easier to run the

test program for the BFMs. In this tutorial, you edit the Qsys testbench system before generating the

simulation model.

Generate Testbench System's Simulation Models

In this section, you open the generated Qsys testbench system and rename the BFM component instance

names to ensure the testbench names match the test program provided with the tutorial design files.

Additionally, you generate the testbench's simulation model.

TU-01006

2015.05.04

Create a New Qsys System for the Design Under Test

Qsys System Design Tutorial

Altera Corporation

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