streaming demultiplexer is soft programmable so that the processor can select which pattern checker IP
core should verify the data that the pattern reader reads. The custom pattern checker is also soft program‐
mable and is configured to match the same pattern as the custom pattern generator.
Refer to the Qsys Memory Tester figure for a graphical description.
Related Information
Qsys System Design Tutorial on page 1
Create a New Qsys System and Set Up the Clock Soource
1. In the Quartus II software, click Tools > Qsys to create a new Qsys design.
2. In the System Contents tab, Qsys shows a clock source instance, clk_0. To open the clock source
settings, right-click clk_0, and then click Edit.
3. Turn off Clock frequency is known to indicate that, when created, the higher-level hierarchical system
that instantiates this subsystem provides the clock frequency.
4. Click Finish.
5. Click File > Save As to save the Qsys system.
6. In the Save As dialog box, type pattern_checker_system, and then click Save.
Add a Pipeline Bridge
1. In the Library search box, type bridge to filter the component list and show only bridge components.
2. Select Avalon-MM Pipeline Bridge, and then click Add.
3. In the parameter editor, under Parameters, type 11 for the Address width.
This width accommodates the memory span of all memory-mapped components behind the bridge in
this system. As you add the other components in the system, you specify their base addresses within
the span of the address space.
4. Accept all other default settings, and then click Finish.
The pipeline bridge is added to your system with the instance name mm_bridge_0.
5. On the System Contents tab, right-click mm_bridge_0, click Rename, and then type mm_bridge.
6. In the Clock column for the mm_bridge clk interface, select clk_0 from the list.
7. To export the mm_bridge s0 interface, double-click the Export column, and then type slave.
Add a Custom Pattern Checker
The custom pattern checker performs the opposite operation of the custom pattern generator. It has a
streaming input interface, st_pattern_input, that accepts data from the one-to-two streaming
demultiplexer. The processor uses the Avalon-MM csr slave interface to control the component. The
custom packet checker also has a memory-mapped slave interface, pattern_access, that the processor uses
to program the same patterns as the custom pattern generator component.
1. In the IP Catalog, expand Memory Test Microcores, and then double-click Custom Pattern Checker.
2. In the parameter editor, accept the default parameters, and then click Finish.
3. Rename the instance to custom_pattern_checker.
4. Set the custom_pattern_checker clock to clk_0.
5. Connect the custom_pattern_checker csr interface to the mm_bridge m0 interface.
6. Connect the custom_pattern_checker pattern_access interface to the mm_bridge m0 interface.
7. Assign the custom_pattern_checker csr interface to a base address of 0x0420.
8. Maintain the custom_pattern_checker pattern_access interface base address of 0x0000.
TU-01006
2015.05.04
Create a New Qsys System and Set Up the Clock Soource
9
Qsys System Design Tutorial
Altera Corporation
Send Feedback
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Comentários a estes Manuais