QSC Q-SYS PS-1650G Manual do Utilizador descarregar pdf (Página 16)

1. In the IP Catalog, double-click Pattern Reader from the Memory Test Microcores group.

2. n the parameter editor, turn on Burst Enable.

3. Ensure the Maximum Burst Count is 2.

4. Ensure that Enable Burst Re-alignment is turned on.

5. To accept the other default parameters, click Finish.

6. Rename the instance to pattern_reader.

7. Set the pattern_reader clock to clk_0.

8. Connect the pattern_reader st_data interface to the pattern_checker_subsystem st_data_in

interface.

9. Export the pattern_reader mm_data interface with the name read_master.

Add a RAM Test Controller

The RAM test controller contains two streaming command interfaces; write_command and

read_command, that send commands to the pattern reader and pattern writer components. These

streaming interfaces issue commands effectively because Avalon-ST interfaces offer low latency and a

simple handshaking protocol, as well as because the processor accesses a slave port, csr, to write

commands to the controller.

1. In the IP Catalog, double-click RAM Test Controller from the Memory Test Microcores group.

2. In the parameter editor, click Finish to accept the default parameters.

3. Rename the instance to ram_test_controller.

4. Set the ram_test_controller clock to clk_0.

5. Connect the ram_test_controller write_command interface to the pattern_writer_command

interface.

6. Connect the ram_test_controller read_command interface to the pattern_reader_command

interface.

7. Connect the ram_test_controller csr interface to the mm_bridge m0 interface.

Do not use the Generation tab at this point in the tutorial to generate HDL code for these subsystems. You

must generate files for the entire top-level system, which includes all the subsystems. The batch script

provided for you to program the device requires that only one system is generated in the project directory.

The top-level design includes a Nios II subsystem, and the Nios II software build tools require the SOPC

Information File (.sopcinfo) to be generated for the top-level design. If there are multiple .sopcinfo files,

the batch script to program the device fails with an error from the software build tools.

Connect the Reset Signals

You must connect all the reset signals, which eliminates the error messages in the Messages tab. Qsys

allows multiple reset domains, or one reset signal for the system. In the design, you want to connect all the

reset signals with the incoming reset signal. To connect all the reset signals, on the System menu, select

Create Global Reset Network.

At this point in the system design, Qsys shows no remaining error messages. If you have any error

messages in the Messages tab, review the procedures to create this system to ensure you did not miss a

step. You can view the reset connections and the timing adapters on the System Contents tab, and by

selecting Show System With Qsys Interconnect on the System menu.

Add a RAM Test Controller

TU-01006

2015.05.04

Altera Corporation

Qsys System Design Tutorial

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